Following the development of the power electronic technology, the required output voltages of certain electronic devices such as the personal computers and the communication devices are relatively lower and the output power of which are relatively higher. The conventional power electronic converter employs at least a diode for the rectification. Obviously, the positive conducting voltage-drop of the diode becomes a main reason to restrict the increase of the efficiency of the converter when the output voltage of which is relatively lower.
To solve the aforementioned problem, a general solution is to replace the diode by a transistor for the rectification, and this is the synchronous rectification technology. Nowadays, the transistors employed for the synchronous rectification are mostly metal-oxide semiconductor field-effect transistors (MOSFETs).
Please refer to FIG. 1, which shows the schematic circuit diagram of a conventional LLC-type series resonant converter (LLC-SRC). The LLC-SRC 10 of FIG. 1 employs the MOSFETs Q1 and Q2 for the synchronous rectification. Referring to FIG. 1, the resonant capacitor Cs and the resonant inductor Ls form a resonant network, Tr is a transformer having a magnetizing inductor Lm at the primary side and a central tap at the secondary side, S1 and S2 are the synchronous rectification transistors at the secondary side of the transformer Tr, D1 and C1 are the parasitic diode and the parasitic capacitor of the SRT S1, D2 and C2 are the parasitic diode and the parasitic capacitor of the SRT S2, and Co is the output capacitor.
The MOSFETs Q1 and Q2 are alternatively turned on and off, and the duty ratio of Q1 and Q2 are both 50%. A positive voltage Vr is added to the resonant network formed by the resonant capacitor Cs and the resonant inductor Ls when the MOSFET Q1 receives a control pulse signal and is turned on, the MOSFET Q2 is turned off, and the polarities of the positive voltage Vr are marked as shown in FIG. 1. At this moment, the SRT S1 at the secondary side of the transformer Tr is turned on, the voltage on the primary side of the transformer Tr is clamped by the output capacitor Co and the resonant capacitor Cs and the resonant inductor Ls are resonant. If the resonant time is less than the turn-on time of the MOSFET Q1, which means the resonant frequency of the LLC-SRC 10 is higher than the working frequency of the same, and the SRT S1 is turned off at the end of the resonance so as to avoid the generation of a reverse current.
By the same token, the SRT S1 is turned on after the MOSFET Q1 is turned off and the MOSFET Q2 is turned on and that is the beginning of the next-half resonant cycle. Also, the SRT S2 is turned off when the resonance is over so as to prevent the generation of a reverse current.
Please refer to FIG. 2, which shows the waveforms of various signals/voltages/currents of switches/resonant network/transformer versus time when the resonant frequency of the conventional LLC-SRC of FIG. 1 is relatively higher than the working frequency of the same. In which, Vgp is the control pulse signal of the MOSFETs Q1 and Q2 on the primary side of the transformer Tr, Vgs is the control pulse signal of the SRTs S1 and S2 on the secondary side of the transformer Tr, Vr is the voltage added on the resonant network (Cs+Ls), ir and im are the resonant current flowing through the resonant network (Cs+Ls) and the magnetizing current of the transformer Tr respectively, and is1 and is2 are the currents flowing through the SRTs S1 and S2 respectively.
As shown in FIG. 2, the MOSFET Q1 at the primary side of the transformer Tr is turned on, the resonant network (Cs+Ls) bears a positive voltage and is resonant, the SRT S1 on the secondary side of the transformer Tr is turned on, and the current flowing through S1 is the difference between the resonant current flowing through the resonant network (Cs+Ls) and the magnetizing current of the transformer Tr (assume that the turns ratio of the transformer Tr is 1:1) during the time period of t0 to t1. At the moment t1, the current flowing through SRT S1 is passing through the zero-crossing point, the SRT S1 is turned off, and the original resonant network (Cs+Ls) and the magnetizing inductor Lm of the transformer Tr form a new resonant network. Due to the resonant period of this new resonant network is relatively quite long, the resonant current flowing through the new resonant network could be viewed as a constant value during the time period of t1 to t3. At the moment t3, the MOSFET Q1 on the primary side of the transformer Tr and the SRT S2 on the secondary side of the transformer Tr are turned on, a negative voltage is added on the resonant network (Cs+Ls), and t3 is the beginning of the next resonant cycle.
Through the operational principles of the LLC-SRC 10, one could tell that the turn-off times of the SRTs on the secondary side of the transformer Tr have to be appropriate controlled such that the whole circuit could operate normally if the LLC-SRC 10 operates under the circumstances that the resonant period of the LLC-SRC 10 is less than the switching period of the same. Two existing controlling methods for the synchronous rectification of the conventional LLC-SRC in the prior art are: (1) Sampling and finding the zero-crossing point of the current flowing through the SRT to turn off the SRT accordingly and (2) Fixing the turn-on time of the SRT.
(1) Sampling and finding the zero-crossing point of the current flowing through the SRT to turn off the SRT accordingly
The first method includes the steps of: (1) sampling the current flowing through the SRTs; and (2) turning off the SRTs at the zero-crossing point of the current flowing through the SRTs. This method has the advantage of realizing the relatively optimized control of the SRTs, and has the disadvantage that the method for sampling the current is relatively more difficult.
(2) Fixing the turn-on time of the SRT
Comparing with the first controlling method, the second controlling method, which includes the step of: fixing the turn-on time of the SRT, is relatively simpler to be accomplished, and has the disadvantage of having a relatively worse capability to adapt and the relatively optimized control of the SRTs could not be reached if the parameters of the SRTs are varied.
Besides, Bridge (U.S. Pat. No. 6,870,747) proposed a third controlling method for the adaptive synchronous rectification, which employs digital controlling method, mainly for controlling the synchronous rectification of the pulse-width modulated (PWM) converter. Through detecting whether the body/parasitic diode of the SRT is conductive or not, the SRT is controlled correspondingly.
Though the above-mentioned third controlling method could realize a relatively better control of the SRT in certain PWM converters, but the aforementioned third controlling method could not accomplish the relatively optimized control of the LLC-SRC. This is because that at the latter half-cycle of the turn-on period of the SRT, the current flowing through the SRT is almost zero such that it is hard to realize the control of the SRT by turning off the SRT at the zero-crossing point of the current on the SRT through detecting whether or not the body/parasitic diode is conductive. Besides, the above-mentioned third controlling method is relatively difficult for applying to the relatively high frequency occasions since the digital controlling method is employed and the counting accuracy of timer is restricted. Furthermore, the turn-off of the SRT has to be executed at the zero-crossing point of the current flowing through the SRT when the PWM converter is working under the discontinuous conduction mode (DCM), and the turn-off of the SRT has no direct connection with the turn-off signal of the main PWM signal. Thus, this third alternative could not achieve the relatively optimized turn-off of the SRT when the converter is working under the DCM.
Please refer to FIG. 3(a), it shows a schematic circuit diagram of the equivalent circuit of the SRT S1/S2. In FIG. 3(a), the transistor has three terminals, the source s, the drain d and the gate g, Cp is the parasitic capacitor between the drain d and the source s, and Dp is the body/parasitic diode. For the PWM converter, the current flowing through the SRT could be viewed as a constant value when the PWM converter is working under the continuous conduction mode (CCM).
FIG. 3(b) is a graph respectively illustrating the waveforms of the source-drain current of the SRT isd, the gate-source voltage Vgs and the drain-source voltage Vds versus time when the PWM converter is working under the CCM. Referring to FIG. 3(b), isd is the source-drain current of the SRT, Vgs is the control pulse signal of the SRT, and Vds is the drain-source voltage drop of the SRT (i.e., the voltage across the parasitic capacitor Cp). As shown in FIG. 3(b), the turn-on time of the SRT is less than the optimized turn-on time of the SRT since the SRT is turned off at the moment t1 when there still is a current flowing through the SRT. In which, the current charges the parasitic capacitor Cp when the SRT is turned off firstly, the voltage across the parasitic capacitor Cp, Vds, is increasing and the slope of this increase is decided by the capacitance of the parasitic capacitor Cp and the value of the current on the SRT. The voltage across the parasitic capacitor Cp, Vds, is clamped by the body diode Dp of the SRT (the parasitic diode) after Vds raises to a certain value, thus the realized value of Vds is the positive voltage drop of the body diode Dp, a current is flowing through the body diode, and the voltage across the parasitic capacitor Cp is maintained at a constant power level. Under such a circumstances, the operational efficiency of the SRT is decreased if the SRT is turned off relatively earlier.
Please refer to FIG. 3(c), which shows a graph respectively illustrating the waveforms of the source-drain current of the SRT isd, the gate-source voltage Vgs and the drain-source voltage Vds versus time when the PWM converter is working under the CCM and the SRT is turned off relatively earlier.
By the same token, the current isd charges the parasitic capacitor Cp when the SRT is turned off at the moment t1. The current isd has a relatively smaller value close to zero, the relatively smaller current isd charges the parasitic capacitor Cp and makes the voltage across the capacitor, Vds, increase slowly, and the slope of Vds is decreased slowly also. At the moment t2, when the current value of isd is at the zero-crossing point, voltage across the parasitic capacitor Cp, Vds, has not reached the clamping value of the body diode Dp yet. Through this procedure, one could tell that the third method proposed by Bridge (U.S. Pat. No. 6,870,747) for controlling the SRT, which is judged by whether or not the body diode Dp is conductive, could not reach the optimized controlling of the SRT.
Please refer to FIG. 3(d), which is a graph respectively illustrating the waveforms of the source-drain current of the SRT isd, the gate-source voltage Vgs and the drain-source voltage Vds versus time when the PWM converter is working under the DCM and the SRT is turned off relatively earlier.
As shown in FIG. 3(d), the current flowing through the SRT isd is decreasing linearly when the SRT is turned off relatively earlier at the moment t1, the relatively smaller current isd will charge the parasitic capacitor Cp, thus the voltage of the parasitic capacitor Cp, Vds, is increased slowly, and the slope of the parasitic capacitor Cp is decreased slowly too. At the moment t2, when the current isd is at the zero-crossing point, the voltage across the parasitic capacitor Cp, Vds, is lower than the voltage clamping value of the body diode Dp. Thus, only through judging whether or not the body diode Dp is conductive when the PWM converter is working under the DCM could not reach the optimized control of the SRT too.
Keeping the drawbacks of the prior arts in mind, and employing experiments and research full-heartily and persistently, the applicant finally conceived the adaptive synchronous rectification control circuit and the method thereof.